FPGA Implementation of Skin Tone Detection Accelerator for Face Detection

Face detection in image sequence has been an active research area in the computer vision field in recent years due to its potential applications such as monitoring and surveillance, human computer interfaces, smart rooms, intelligent robots, and biomedical image analysis. Face detection is based on identifying and locating a human face in images regardless of size, position, and condition. An algorithm for Skin tone Detection Accelector has been implemented for colour images in the presence of varying lighting conditions as well as complex backgrounds and it detects skin regions over the entire image, and then generates face candidates based on the spatial arrangement of these skin patches .The algorithm constructs eye, mouth, and boundary maps for verifying each face candidate. The proposed architecture of Skin tone detection Accelerator for Face detection has been designed using Verilog HDL, simulated using ISE simulator and implemented in Xilinx FPGA module. Its performance has been improved when compared with an equivalent software implementation